The present invention relates to semiconductor devices, and more specifically, to a vertical field effect transistor (VFET) having uniform spacers and methods of fabricating the same.
A VFET has a channel perpendicular to the substrate surface, as opposed to a conventional FET, which has a channel extending substantially along the plane of the surface of the device substrate. By using this vertical channel design, it is possible to increase packing density. That is, by forming the channel substantially perpendicular to the substrate surface, VFETs improve the scaling limit beyond FET devices that have their channels positioned substantially parallel to the substrate surface. However, aspects of forming VFETs are challenging as semiconductor fabrication processes move past 7 nm node spacing. In general, the term “node” refers to the major targets or features in a fabrication roadmap. Thus, the phrase “7 nm node” means that the smallest spacing between repeated features on a chip along one direction is 7 nm. Conventional FET sidewall spacer formation can use deposition followed by reactive ion etching, for example. However, this mode of spacer formation is not possible in VFET manufacture due to the horizontal spacer arrangement. Accordingly, spacer formation in vertical FET fabrication can be challenging.